(1) Field of the Invention
The present invention relates generally to electrically rewritable nonvolatile semiconductor memories (hereinafter simply referred to as nonvolatile memories) such as E.sup.2 PROMs, flash memories, and the like, and more particularly to a nonvolatile memory having an increased operating speeds and capable of providing accurate readout even at power-on.
(2) Description of the Related Art
Electrically rewritable nonvolatile memories include, for example, E.sup.2 PROM, and flash memory having total or selective total erasure capabilities. Flash memory has been attracting attention in recent years because of its high bit-density capabilities. The present invention is applicable to electrically rewritable nonvolatile memories of all types. In the following description, however, the flash memory is used as a representative example.
The nonvolatile memory cell has a two-layer gate structure consisting of a control gate and a floating gate, in which information storage is accomplished by utilizing the property that when prescribed voltages are applied to the control gate, drain, and source, the current flowing between the drain and the source varies depending on whether or not a charge is stored on the floating gate. Generally, in flash memories, injecting a charge into the floating gate is called writing, and extracting a charge from the floating gate is called erasure.
Usually, in flash memories, when data is rewritten, i.e., in data erase and write operations, in order to ensure the accuracy of the rewrite operation, a read operation is performed, for verification of the rewritten data, after performing the rewrite operation.
For flash memories, specifications are provided, such as the supply voltage limits within which proper operation of the device is guaranteed, and the guaranteed period and operating time for reliable retention of stored data. For the device to operate properly within the limits provided by the specification, it is required that the stored data have such a margin that it can be read out correctly under the worst conditions. Also, to guarantee the reliable retention of the stored data for long periods of time, the data needs to be provided with such a margin as to prevent the evaluation of its logic value from being affected by any change that may occur under the worst conditions during the retention period thereof, such changes including charge leakage and charge injection that may occur on the floating gate, whatever the cause.
Therefore, in flash memories, stricter conditions are placed on the voltage applied to the control gate for the verify operation than for normal operations, to confirm that the rewritten data has a reliable margin. More specifically, in a write verify operation, the voltage applied to the control gate is set at about 6.5 V, which is higher than the voltage normally applied, and it is determined whether the logic value "L" can still be output at that voltage. In an erasure verify operation, the voltage applied to the control gate is set at about 3.5 V, which is lower than the voltage normally applied, and it is determined whether the logic value "H" can still be output at that voltage. The voltage applied to the control gate for a verify operation is called the verify voltage, and in this specification also, this term is used.
As efforts continue to produce higher density flash memories, the memory cell size is becoming increasingly smaller, which tends to cause the memory cell driving capabilities to drop. On the other hand, higher operating speeds are demanded of the device. One approach to addressing this demand is to employ a method of increasing operating speeds, widely used in asynchronous memories, which involves performing operations such as bit line charge-up after detecting an address signal change. An address-transition-detection circuit (hereinafter referred to the ATD circuit) is used to detect an address signal change.
Furthermore, nonvolatile memories such as flash memories are required, by the nature of their characteristics, to ensure proper data readout at power-on in accordance with the input conditions set at that time, which requires that the same operation performed when an address signal change has occurred be performed when the turning on of the power is detected.
When a flash memory is equipped with an ATD circuit and designed to perform the same operation when power is turned on as when an address signal change has occurred, a problem specific to flash memory will arise because flash memory is erasable. Generally, the supply voltage level detected as power-on is about 3 V.
On the other hand, the verify voltage for erasure is about 3.5 V. This means that a memory cell verified as erased in a verify operation may output data "L" at the time of power-on if the threshold voltage is somewhere between 3 V and 3.5 V. That is, the memory cell, though it has been erased, may be judged as being in a written state. Such an error is a serious problem as it degrades the reliability of the memory device.